The present disclosures relate to semiconductor structures, and more particularly, to a process and structure of a III-V compound semiconductor heterostructure MOSFET.
In III-V compound semiconductor process technology, there exists a need for a compound semiconductor heterostructure MOSFET process flow that facilitates the use of a GdGaO/Ga2O3 dielectric stack as a gate oxide. In addition, in an absence thereof, there is a need for an implant-free enhancement mode structure and process. Some examples of implant free MOSFETs are discussed in a co-pending patent application Ser. No. 10/339,379, entitled “An Enhancement mode Metal-Oxide-Semiconductor Field Effect Transistor,” Matthias Passlack et al., filed Jan. 9, 2003, and are not discussed further here.
Accordingly, there is a need for an improved method and apparatus for overcoming the problems in the art.
The use of the same reference symbols in different drawings indicates similar or identical items. Skilled artisans will also appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.